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Sr Design Verification Engineer

Location
San Francisco, California
Posted
7 Sep 2022

Job description

Create verification plans for complex processor systems and IP blocks

Create testbenches in SystemVerilog with UVM

Utilize advanced verification techniques

Write tools and scripts to enhance the verification process

Qualifications and requirements:

5+ years industry experience required

BS, MS in computer science or engineering

Experience with C/C++

Experience with SystemVerilog and UVM

Some level of processor based verification

Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers

Experience with tools for regression management, configuration management and bug tracking

Good software skills

Good problem solving and debugging skills

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Details

  • Job Reference: 706060284-2
  • Date Posted: 7 September 2022
  • Recruiter: Nano Executive Search Group LLC
  • Location: San Francisco, California
  • Salary: On Application